The present invention relates to a logic circuit such as a BDD logic circuit or D latch logic circuit which greatly reduces the power consumption and the circuit size by performing adiabatic charging logic using a supply voltage whose waveform moderately rises and falls.
An adiabatic charging logic method has received attention as a method of performing logic processing with low power consumption. One of the characteristics of this adiabatic charging logic method is that the supply voltage moderately and periodically changes (moderately rises and falls).
Assume that the supply voltage rises from Low (low voltage level) to High (high voltage level) sufficiently slowly as compared with the RC time constant of an inverter serving as a logic circuit. In this case, it is known that the work done by the supply voltage is 1/2.multidot.CV.sup.2, which coincides with the energy stored in a load capacitance. It is also known that when the supply voltage changes from High to Low, the energy stored in the load capacitance is not discharged to ground (GND) but returns to the power supply circuit (charger recycling), thereby ideally performing logic processing of "Low.fwdarw.High.fwdarw.Low" with almost no consumption of energy (reference 1: "Energy-Recovery CMOS" William C. Athas, LOW POWER DESIGN METHODOLOGIES, edited by J. M. Rabaey et al., KLUWER ACADEMIC PUBLISHERS, pp. 66-72, 1996).
As a power supply circuit for implementing this logic, an AC circuit using an inductor and a capacitor is available. The inductor and the capacitor constitute a resonance circuit to generate an AC voltage. By using this circuit as a charge recycle generator, adiabatic charging and charge recycling can be performed.
A circuit that uses N-1 capacitors to generate an N-step staircase voltage (a voltage that changes/rises in N steps and changes/falls in N steps) is also known (reference 1). With this circuit as well, adiabatic charging and charge recycling can be performed.
When, however, adiabatic charging or charge recycling is to be performed in a general CMOS circuit by using a charge recycle generator, even if the rise/fall timing of an output voltage from the charge recycle generator is properly adjusted for one logic gate, the rise/fall timing must be adjusted again for the logic gate on the next stage.
A transmission gate type retractile logic circuit, which differs from the above CMOS circuit but is known as a circuit capable of easily realizing adiabatic charging and charge recycling, will be described below as an example of how the timing is difficult to adjust.
FIG. 63A shows this retractile logic circuit. Reference numerals 501 to 504 denote logic gates; and 505 and 506, capacitors. This circuit receives input signals A and B, performs AND logic (=A.multidot.B) processing for the input signals, and obtains the OR logic (=A.multidot.B+C) of the AND logic processing result and an input signal C. As a logic gate of this retractile logic circuit, a two-wire logic element using transmission gates 507 has been proposed, as shown in FIGS. 64B and 64C. This element receives complementary input signals A and *A and complementary input signals B and *B and outputs output signals A.multidot.B and *(A.multidot.B). Note that the symbol "*" indicates that the corresponding signal is an inverted signal.
In this retractile logic circuit, the waveforms of supply voltage V1 and V2 are controlled in accordance with the number of gates, as shown in the timing charts of FIGS. 63B to 63F. More specifically, control must be performed to cause the supply voltage V1 to moderately (with a constant slope) rise later and fall earlier than the input signals A and B. The same applies to the relationship between the input signal C and the supply voltage V2.
FIGS. 65A and 65B show a conventional BDD logic circuit. As shown in FIG. 65A, the BDD graph (Binary Decision Diagram) used for this logic circuit is a graph having beginning points 1 and 2 and ending points 3 and 4. Input variables (A, B, and C in FIG. 65A) correspond to nodes 5. When the value of a logic output is to be obtained from supplied input variable values, the input enters from the beginning point 1 or 2 of the graph, goes down along the respective nodes 5, and reaches one of the two ending points 3 and 4. At each node 5, the input goes along one of two branches 6 and 7 in accordance with the input variable value. If, for example, the input variable C is "0", the input goes along 0 branch 6. If C="1", the input goes along 1 branch 7. That is, when an input is supplied, one path from a beginning point to an ending point is designated. If the ending point of the path is "0", the logic output becomes "0". If the ending point is "1", the logic output becomes "1".
In the BDD logic circuit, as shown in FIG. 65B, logic elements that satisfy the above conditions, e.g., N-channel MOSFETs 8 and wires 9, are made to correspond to the respective branches of the BDD on the basis of the BDD graph shown in FIG. 65A. In addition, logic outputs are made to correspond to the beginning points 1 and 2 of the BDD graph. Furthermore, ground (GND) is connected to the ending point 3 of "0" of the BDD graph, and a constant supply voltage VDD is connected to the ending point 4 of "1" of the BDD graph (reference 2: Kuroda and Sakurai, "Overview of Low-Power ULSI Circuit Techniques" IEICE TRANS. ELECTRON., Vol. E78-C, NO. 4 April 1995, pp. 334-344).
FIG. 66 shows the arrangement of a conventional D latch logic circuit. This logic circuit is made up of two transmission gates 601 and 602 constituting a data receiving circuit, and transmission gates 603 and 604 and inverters 605 and 606 which are cross-connected to constitute a storage circuit. A clock signal CK and an inverted signal *CK thereof are input to the transmission gates 601 to 604, and constant supply voltages VDD are applied to the inverters 605 and 606.
In this D latch logic circuit, when the clock signal CK is at High, the signals input to nodes 607 and 608 respectively reach nodes 609 and 610 through the transmission gates 601 and 602 and inverted by the inverters 605 and 606. The resultant signals are then output to nodes 611 and 612. When the clock signal CK changes to Low, the nodes 610 and 611 are connected to each other, and the nodes 609 and 612 are connected to each other. As a result, the output signals from the inverters 605 and 606 are supplied to the input sides of the inverters 605 and 606 on the opposite sides. The output signals are held until the clock signal CK is set at High again (storage mode) .
A wire 400 in FIG. 67, which is used in a conventional CMOS logic circuit such as a combinational logic circuit or a D latch logic circuit, has a large cross-sectional area to drive the gate on the next stage at a high speed on the order of PS. As shown in FIG. 67, this wire cross-sectional area is 550 nm (0.55 .mu.m: signal wire width W.sub.0).times.550 nm (0.55 .mu.m: signal wire thickness H.sub.o) in the 0.25 .mu.m process of Nippon Telegraph and Telephone Corporation (NTT). In this case, the CR time constant is about 0.5 ns.
In the above retractile logic circuit, as the number of gates increase to several hundreds and several thousands, several hundred and several thousand supply voltage waveforms must be controlled. If, therefore, adiabatic charging and charge recycling are performed by using a charge recycle generator, the power consumption increases contrarily.
In the D latch logic circuit, at a transmission gate portion, charging/discharging must be performed with respect to the gate of a MOSFET as an element of the transmission gate or a clock signal line. In this charging/discharging operation, the energy corresponding to C.sub.TG VDD.sup.2 (where VDD is the supply voltage and C.sub.TG is the sum of the gate capacitance of the transmission gate and the capacitance of the clock signal line) is consumed. In the storage circuit as well, the energy corresponding to C.sub.ME VDD.sup.2 (where C.sub.ME is the capacitance of the storage circuit) is consumed.
In the conventional CMOS logic circuit, since the wire cross-sectional area is set to be large, it is difficult to reduce the circuit size. In addition, the self-capacitance of each wire and the mutual capacitance between the wires cannot be reduced.